The present invention relates to a lateral field effect transistor of SiC for high switching frequencies comprising a source region layer and a drain region layer laterally spaced and highly doped n-type, an n-type channel layer of lower doping concentration extending laterally and interconnecting the source region layer and the drain region layer for conducting a current between these layers in the on-state of the transistor, and a gate electrode arranged to control the properties of the channel layer to be conducting or blocking through varying the potential applied to the gate electrode.
"High switching frequencies" means here frequencies above 1 MHz. Such transistors may be used in for instance power microwave applications in for example base stations for mobile telephones, radars and microwave ovens.
High frequency field effect transistors of this type require short gate electrodes in order to increase on-state channel current, minimize the carrier transit time in the channel and. the gate capacitance. Shorter gate electrodes will therefore result in higher power and higher operation frequency. On the other hand, undesirable short-channel effects become significant as the gate length is decreased. Transistors with very short gates often do not show saturation in drain current with increasing drain bias, and a continual increase in drain current with increasing the drain bias is observed instead. This occurs because of the channel length modulation by the drain bias. Furthermore, in the extreme case a parasitic bipolar transistor can be turned on at a high drain bias, in which the source and drain act as the collector and emitter of the parasitic transistor, and the layer next to the channel layer, which is a substrate or buffer layer, is then the base. This effect may not be particularly significant for low power high frequency transistors, but it increasingly dominates the performance of high power transistors, in which the drain bias should be as high as possible in order to increase the total power.
Silicon carbide has, as a material for high frequency power transistor applications a number of advantages with respect to for instance Si. It has a high breakdown field, which results in a possibility to have shorter carrier transit times, a high saturation drift velocity and a high thermal conductivity.
A transistor of the type defined in the introduction is known through for instance U.S. Pat. No. 5,270,554, which describes a high frequency field effect transistor with a lateral n-type channel. A channel of n-type conductivity is preferred, because the mobility of free electrons is considerably higher than valence-band holes in SiC. This transistor already known has a conductive substrate, a p-type buffer layer on top thereof, an n-type channel layer and highly doped contact regions formed in order to decrease the resistance of the drain and source region layers, as well as to minimise the contact resistance of these layers. The buffer layer of this transistor has to be low-doped and thick in order to block high voltages, minimise high-frequency active losses due to conductance and minimise reactive losses due to internal capacitances. This type of design is particularly prone to short-channel effects and a parasitic bipolar transistor turns on at large drain bias, said buffer layer functioning as the base of such a bipolar transistor. Such effects may be suppressed by increasing the gate length, but that would deteriorate the on-state current and high-frequency performance.
Accordingly, lateral field effect transistors of SiC for high switching frequencies experience undesirable short-channel effects if a short gate electrode is formed. The values of gate length, which can be achieved using currently available pattern definition tools are coniderably below those, which are required for blocking a high voltage, which means that such high frequency transistors do not utilise the material potential to the full extent.